1. Field of the Invention
The present invention relates to a semiconductor device process, more specifically, to a test mask structure, which is able to promote etching accuracy.
2. Description of the Prior Art
In the semiconductor device process, the formation of the respective parts of the integrated circuit frequently utilizes mask etch techniques. However, in the respective steps of pattern setting, mask producing, exposing, developing, imaging and etching, due to the material and errors from practical operation, predetermined critical dimension cannot be maintained a hundred percent in each step. Taking a pattern of 180 nm critical dimension as an example, the critical dimension is set as 180 nm in the initial layout. However, in consideration of the possible errors, which may occur in the subsequent process, when making a mask, the critical dimension is maintained as 180 nm in high pattern density portion, while the critical dimension is increased to 200 nm in middle density portion and increased to 220 nm in low density portion, so as to expect the critical dimension in the respective portions of different pattern densities for a final etched pattern can be maintained as 180 nm. However, in the final etched pattern, it is possible that the critical dimension in the middle density portion is 190 nm, and the critical dimension in the low density portion is 200 nm. Accordingly, it is necessary to adjust the settings for the critical dimension in the respective portions. For example, the critical dimension is respectively adjusted to 190 nm and 200 nm for the middle density portion and the low density portion of the mask. To properly determine the required critical dimension settings for producing masks, it is necessary to perform testing using a test mask before production so as to get the data of the errors generated during the interval from applying a mask to completing etching.
FIG. 1 illustrates a conventionally used test mask structure. The pattern density distribution of the conventional test mask is gradually from high to low from one side to the other side. For a 110 nm test mask, the average density of the entire test mask is 32.2%.
However, for a practical product of 110 nm dimension, the pattern density is about 50%, usually 45˜48%. Due to the difference between the pattern densities, the margin adjustment made base on the data obtained by using the test mask is not sufficiently accurate, causing the profile of the final etched product degraded.
Therefore, there is a need for a solution to overcome the problems stated above. The present invention satisfies such a need.